1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor device including a plurality of circuit blocks that need to have exactly the same operation timing.
2. Description of Related Art
Some semiconductor devices include a plurality of circuit blocks that need to have exactly the same operation timing. Among examples of such circuit blocks are data input/output circuits. A data input/output circuit is connected to a data pad or chip pad that is connected to an external terminal of the semiconductor device. Data input/output circuits need to simultaneously supply input data supplied to a plurality of data pads in parallel to an internal circuit, and simultaneously supply output data output from an internal circuit in parallel to the plurality of data pads. For this purpose, a plurality of data input/output circuits need to have exactly the same operation timing.
Some semiconductor devices have a large number of data pads, which are not always possible to arrange in a row. In such a case, data pads may be arranged in two rows, and a plurality of data input/output circuits having the same pattern layout may be arranged between and along the two rows of data pads (see Japanese Patent Application Laid-Open No. 2011-060909). The data input/output circuits assigned to one of the rows of data pads and those assigned to the other row of data pads may be symmetrically arranged with respect to the center line of the two rows of data pads. A timing signal may be supplied to the plurality of data input/output circuits in common.
Now, suppose that data input/output circuits having the same layout are symmetrically arranged as described above. Although a common timing signal is supplied to the plurality of data input/output circuits, the symmetrically-arranged circuits to which the timing signal is supplied may be at a distance from each other. In such a case, wiring for supplying the timing signal to the data input/output circuits assigned to one of the rows of data pads needs to branch off from wiring for supplying the timing signal to the data input/output circuits assigned to the other row of data pads. The branches have different time constants depending on the wiring length. Consequently, the data input/output circuits can vary in operation timing due to the differences in wiring length. If there is a large difference in operation timing, design needs to be tailored to a data input/output circuit that operates the slowest. This causes a hindrance to high speed operations. The branched wiring also increases the load of the timing signal itself, which hinders speedup.